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ASAHI KASEI
[AK4342]
AK4342
24-Bit Stereo DAC with HP-AMP & 2V Line-Out
GENERAL DESCRIPTION The AK4342 is a 24-bit stereo DAC with 2Vrms lineout, an integrated headphone amplifier, and an auxiliary line output. The AK4342 features an analog mixing circuit that enables a simple interface to external analog audio sources. The integrated headphone amplifier features "click-free" power-on/off, a mute control and delivers 62.5mW of power at 16 @ 3.3V. The AK4342 is controlled via an I2C or 3-wire interface, and is available in a 32-pin QFN package. FEATURE Multi-bit 24-bit DAC Sampling Rate: 8kHz to 96kHz 8 times Oversampling FIR interpolator - Passband: 20kHz - Passband Ripple: 0.02dB - Stopband Attenuation: 54dB Audio I/F Format: MSB First, 2's Complement - I2S, 24bit MSB justified, 24bit/20bit/16bit LSB justified Master Clock: - Normal Speed Mode: 256fs/384fs/512fs/768fs - Double Speed Mode: 128fs/192fs/256fs/384fs - Half Speed Mode: 512fs/768fs Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz Analog volume control: - Headphone: +6dB to - 48dB, Variable Step Size - Lineout: 0dB to - 31dB, 1dB step Digital Linear Attenuator Digital Soft Mute Analog Mixing Circuit P Interface: 3-wire/I2C (400kHz mode) Pop Noise Free at Power-ON/OFF and Mute DAC Performance (Lineout) - THD+N: -88dB - Dynamic Range: 100dB - Output Level: 2Vrms DAC Performance (Aux-Out) - THD+N: -87dB - Dynamic Range: 95dB Headphone Amplifier (Cap-less) - Output Power: 62.5mW x 2ch @16, 3.3V - THD+N: -60dB @ 25mW - Dynamic Range: 95dB Power Supply: - DAC & Output Buffers: 2.7V 3.6V - Digital Interface: 1.6V 3.6V Power Supply Current: 30.5mA (Headphone amp off) Ta: -30 85C Package: 32pin QFN
MS0506-E-02 -1-
2006/07
ASAHI KASEI
[AK4342]
MCLK
LIN
HVDD
HVSS
HVEE VCOM
BICK LRCK SDATA
VCOM Audio Interface Clock Divider VOL MUTE
HPL
DAC
(Lch)
VOL MUTE
PMHP
HPR
ATT & Soft Mute
DEM & Digital Filter DAC
(Rch)
VOL MUTE VOL MUTE
PMLO
LOUT
ROUT
PDN I2C CAD0/CSN SCL/CCLK SDA/CDTI Serial I/F
PMDAC
PVDD PVSS Charge Pump PVEE CP
PMCP
CN LAUX RAUX
PMAUX
MUTE MUTE
TVDD
DVDD
DVSS
AVDD
AVSS
RIN
MUTET
Figure 1. AK4342 Block Diagram
MS0506-E-02 -2-
2006/07
ASAHI KASEI
[AK4342]
Ordering Guide
AK4342EN AKD4342 32pin QFN (0.5mm pitch) -30 +85C Evaluation board for AK4342
Pin Layout
18
24
23
22
21
20
MUTET VCOM AVDD AVSS DVSS DVDD TVDD I2C
19
17
HVDD
ROUT
RAUX
HVSS
LOUT
LAUX
RIN
LIN
25 26 27 28 29 30 31 32 7 1 2 3 4 5 6 8
16 15 14
HPR HPL HVEE PVEE PVSS PVDD CN CP
AK4342EN
Top View
13 12 11 10 9
SCL/CCLK
BICK
SDA/CDTI
LRCK
MCLK
MS0506-E-02 -3-
CAD0/CSN
SDATA
PDN
2006/07
ASAHI KASEI
[AK4342]
PIN/FUNCTION
No. 1 Function Control Data Input/Output Pin (I2C pin = "H") SDA I/O An external pull-up resister is required. CDTI I Control Data Input Pin (I2C pin = "L") Control Data Clock Pin (I2C pin = "H") SCL I An external pull-up resistor is required. CCLK I Control Data Clock Pin (I2C pin = "L") CAD0 I Chip Address 0 Select Pin (I2C pin = "H") (Internal Pull-up Pin to TVDD pin) CSN I Control Data Chip Select Pin (I2C pin = "L") (Internal Pull-up Pin to TVDD pin) MCLK I Master Clock Input Pin Serial Bit Clock Pin BICK I This clock is used to latch audio data. L/R Clock Pin LRCK I This clock determines which audio channel is currently being input on SDATA pin. SDATA I Audio Serial Data Input Pin Power-down & Reset Pin PDN I When at "L", the AK4342 is in power-down mode and is held in reset. The AK4342 must be reset once upon power-up. CP O Positive Charge Pump Capacitor Terminal Pin CN I Negative Charge Pump Capacitor Terminal Pin PVDD Charge Pump Circuit Positive Power Supply Pin PVSS Charge Pump Circuit Ground Pin PVEE O Charge Pump Circuit Negative Voltage Output Pin Headphone Amp Negative Power Supply Pin HVEE Connected to PVEE pin HPL O Lch Headphone Amp Output Pin HPR O Rch Headphone Amp Output Pin HVDD Headphone Amp Positive Power Supply Pin HVSS Headphone Amp Ground Pin LOUT O Lch Lineout Output Pin ROUT O Rch Lineout Output Pin LAUX O Lch Auxiliary Output Pin RAUX O Rch Auxiliary Output Pin LIN I Lch Analog Input Pin RIN I Rch Analog Input Pin Mute Time Constant Control Pin MUTET O Connected to AVSS pin through a 1F capacitor for mute time constant. Common Voltage Output Pin VCOM O Normally connected to AVSS pin with 0.1F ceramic capacitor in parallel with a 2.2F electrolytic capacitor. AVDD Analog Power Supply Pin AVSS Analog Ground Pin DVSS Digital Ground Pin DVDD Digital Power Supply Pin TVDD Digital Interface Power Supply Pin Control Mode Select Pin (Internal Pull-up Pin to TVDD pin) I2C I "H": I2C Bus, "L": 3-wire Serial Do not allow digital input pins except analog input pins (RIN and LIN) and internal pull-up pins (CAD0/CSN and I2C) to float. Pin Name I/O
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note:
MS0506-E-02 -4-
2006/07
ASAHI KASEI
[AK4342]
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below. Classification Analog Pin Name MUTET, HPL, HPR, LOUT, ROUT, LAUX, RAUX, RIN, LIN Setting These pins should be open.
MS0506-E-02 -5-
2006/07
ASAHI KASEI
[AK4342]
ABSOLUTE MAXIMUM RATING (AVSS, DVSS, HVSS, PVSS = 0V; Note 1) Parameter Symbol min max Units Power Supplies Analog 4.0 V AVDD -0.3 4.0 V Digital DVDD -0.3 4.0 V HP-Amp HVDD -0.3 Charge Pump PVDD 4.0 V -0.3 Digital I/F TVDD 4.0 V -0.3 |AVSS - DVSS | (Note 2) 0.3 V GND1 |AVSS - HVSS | (Note 2) 0.3 V GND2 |AVSS - PVSS | (Note 2) 0.3 V GND3 Input Current (any pins except for supplies) IIN mA 10 Analog Input Voltage (Note 3) AVIN AVDD+0.3 or 4.0 V -0.3 Digital Input Voltage (Note 4) DVIN TVDD+0.3 or 4.0 V -0.3 Ambient Temperature Ta 85 -30 C Storage Temperature Tstg 150 -65 C Maximum Power Dissipation (Note 5) Pd 700 mW Note 1. All voltages with respect to ground. Note 2. AVSS, DVSS, HVSS and PVSS must be connected to the same analog plane. Note 3. LIN and RIN pins. The maximum value is low value either "AVDD+0.3V" or "4.0V". Note 4. MCLK, BICK, LRCK, SDATA, CAD0/CSN, SCL/CCLK, SDA/CDTI, I2C and PDN pins. The maximum value is low value either "TVDD+0.3V" or "4.0V". Pull-up resistors at SDA and SCL pins should be connected to (TVDD+0.3)V or less voltage. Note 5. In case that PCB wiring density is 100%. This power is the AK4342 internal dissipation that does not include power of externally connected headphone.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMEND OPERATING CONDITIONS (AVSS, DVSS, HVSS, PVSS = 0V; Note 1) Parameter Symbol min typ Power Supplies Analog AVDD 2.7 3.3 ( Note 6) Digital DVDD 2.7 3.3 HP-Amp HVDD 2.7 3.3 Charge Pump PVDD 2.7 3.3 Digital I/F TVDD 1.6 1.8 DVDD - AVDD -0.3 0 Difference DVDD - HVDD -0.3 0 DVDD - PVDD -0.3 0 Note 1. All voltages with respect to ground.
max 3.6 3.6 3.6 3.6 DVDD 0.3 0.3 0.3
Units V V V V V V V V
Note 6. Power up sequence among AVDD, DVDD, HVDD, PVDD and TVDD is not critical. But PDN pin must keep "L" until all power supply pins are applied. After that, PDN pin should be set to "H". Each power supply cannot be partially powered OFF. * AKM assumes no responsibility for usage beyond the conditions in this datasheet.
MS0506-E-02 -6-
2006/07
ASAHI KASEI
[AK4342]
ANALOG CHARACTERISTICS (Ta=25C; AVDD=DVDD=HVDD=PVDD=3.3V, TVDD=1.8V, AVSS=DVSS=HVSS=PVSS=0V; fs=44.1kHz; Signal Frequency =1kHz; Measurement band width=10Hz 20kHz; Headphone-Amp: RL =16; Line output: RL =10k, Aux output: RL =10k; Charge Pump Circuit External Capacitance: C1=C2= 2.2F (see Figure 2); unless otherwise specified) Parameter min typ max Units 24 bit DAC Resolution LINEIN: (LIN/RIN pins) Analog Input Characteristics: Maximum Input Voltage (Note 7) 1.98 Vpp Feedback Resistance 14 20 26 k Gain (LIN/RIN pins: External resistor = 20k) (Note 8) Vin = 1Vpp LIN/RIN HPL/HPR (Note 9) 1.5 4.5 dB -1.5 4.5 7.5 10.5 dB LIN/RIN LOUT/ROUT (Note 10) 1.3 dB LIN/RIN LAUX/RAUX -4.7 -1.7 Headphone-Amp: (DAC HPL/HPR pins) (Note 11) Analog Output Characteristics dB THD+N fs=44.1kHz 0dBFS Output, Po=62.5mW -40 BW=20kHz -4dBFS Output, Po=25mW dB -60 -50 dB fs=96kHz 0dBFS Output, Po=62.5mW -40 BW=40kHz -4dBFS Output, Po=25mW dB -60 -50 87 95 dB Dynamic Range (-60dBFS Output, A-weighted) S/N (A-weighted) 87 95 dB Interchannel Isolation 60 80 dB DC Accuracy Interchannel Gain Mismatch 0.2 1.0 dB Gain Drift 200 ppm/C Load Resistance 16 Load Capacitance 300 pF Output Voltage (0dBFS Output) (Note 12) 0.9 1.0 1.1 Vrms Line Output: (DAC LOUT/ROUT pins) (Note 13) Analog Output Characteristics dB THD+N fs=44.1kHz 0dBFS Output -88 -78 dB BW=20kHz -60dBFS Output -37 fs=96kHz 0dBFS Output dB -88 -78 BW=40kHz -60dBFS Output dB -35 92 100 dB Dynamic Range (-60dBFS Output, A-weighted) S/N (A-weighted) 92 100 dB Interchannel Isolation 80 100 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.8 dB Gain Drift 200 ppm/C Load Resistance 10 k Load Capacitance (C3 in Figure 3) 25 pF Output Voltage (Note 14) 1.8 2.0 2.2 Vrms
MS0506-E-02 -7-
2006/07
ASAHI KASEI
[AK4342]
Note 7. Maximum Input Voltage of LIN/RIN pins is proportional to AVDD voltage. Since the internal feedback resistor is 20k30%, the external resistor should determine that the value does not exceed the maximum input voltage. Note 8. The gain is inverse proportion to external input resistance. Note 9. PGAL4-0=PGAR4-0= 0dB Note 10. LPGA4-0= 0dB Note 11. PMVCM=PMCP=PMDAC=PMHP bits = "1", PMLO=PMAUX bits= "0", LINL=LINR=RINL=RINR bits = "0", ATTL7-0=ATTR7-0= 0dB, PGAL4-0=PGAR4-0= 0dB. Note 12. Output voltage is proportional to AVDD voltage. Vout (typ.) = 0.303 x AVDD [Vrms] @ 0dBFS Note 13. PMVCM=PMCP=PMDAC=PMLO bits = "1", PMHP=PMAUX bits= "0", LINL=LINR=RINL=RINR bits = "0", ATTL7-0=ATTR7-0= 0dB, LPGA4-0= 0dB. Note 14. Output voltage is proportional to AVDD voltage. Vout (typ.) = 0.606 x AVDD [Vrms] @ 0dBFS
HVEE pin
To headphone and lineout amps
PVEE pin C1 CN pin Charge Pump Circuit CP pin PVSS C2
Figure 2. Charge Pump Circuit External Capacitor
LOUT/ROUT pin
Analog Out
C3
Figure 3. Line out circuit example
MS0506-E-02 -8-
2006/07
ASAHI KASEI
[AK4342]
Parameter min typ max Units Aux Output: (DAC LAUX/RAUX pins) (Note 15) Analog Output Characteristics THD+N fs=44.1kHz 0dBFS Output dB -87 -77 dB BW=20kHz -60dBFS Output -32 fs=96kHz 0dBFS Output dB -87 -77 dB BW=40kHz -60dBFS Output -30 87 95 dB Dynamic Range (-60dBFS Output, A-weighted) S/N (A-weighted) 87 95 dB Interchannel Isolation 80 100 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.8 dB Gain Drift 200 ppm/C Load Resistance (Note 16) 10 k Load Capacitance (C4 in Figure 4) 25 pF Output Voltage (Note 17) 0.63 0.70 0.77 Vrms Output Volume for Headphone-amp (PGAL, PGAR): Step Size +6dB to -10dB 0.1 1 1.9 dB -10dB to -32dB 0.1 2 3.9 dB -32dB to -48dB 0.1 4 7.9 dB Output Volume for Lineout-amp (LPGA): Step Size 0dB to -31dB 0.1 1 1.9 dB Power Supplies Power Supply Current Normal Operation (PDN pin = "H") (Note 18) AVDD+HVDD+PVDD 28 45 mA DVDD+TVDD (fs = 44.1kHz) 2.5 4 mA DVDD+TVDD (fs = 96kHz) 3.5 5.5 mA Power-Down Mode (PDN pin = "L") (Note 19) AVDD+HVDD+PVDD+DVDD+TVDD 10 100 A Note 15. PMVCM=PMDAC=PMAUX bits = "1", PMHP=PMLO bits= "0", LINL=LINR=RINL=RINR bits = "0", ATTL7-0=ATTR7-0= 0dB Note 16. For AC load Note 17. Output voltage is proportional to AVDD voltage. Vout (typ) = 0.212 x AVDD [Vrms] @ 0dBFS Note 18. PMVCM=PMDAC=PMHP=PMLO=PMAUX bits = "1" and HP-Amp output is off. Note 19. All digital input pins including clock pins (MCLK, BICK and LRCK) except I2C and CSN/CAD0 pins are held at DVSS. I2C and CSN/CAD0 pins are held at TVDD.
LAUX/RAUX pin
Analog Out
C4
Figure 4. Aux-out circuit example
MS0506-E-02 -9-
2006/07
ASAHI KASEI
[AK4342]
FILTER CHARACTERISTICS (Ta=25C; AVDD, DVDD, HVDD, PVDD=2.7 3.6V, TVDD=1.6 3.6V; fs=44.1kHz; De-emphasis = "OFF") Parameter Symbol min typ max Units DAC Digital Filter: PB 0 20.0 kHz Passband 0.05dB (Note 20) 22.05 kHz -6.0dB Stopband (Note 20) SB 24.1 kHz Passband Ripple PR dB 0.02 Stopband Attenuation SA 54 dB Group Delay (Note 21) GD 21 1/fs Group Delay Distortion 0 s GD Digital Filter + Analog Filter: (Note 22) dB Frequency Response 20.0kHz (fs=44.1kHz) FR -0.5 dB 40.0kHz (fs=96kHz) FR -1.5 Analog Filter: (Note 23) dB Frequency Response 20.0kHz FR 1.0 dB 40.0kHz FR 1.0 Note 20. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@0.05dB), SB=0.546*fs(@-54dB). Note 21. Delay time caused by digital filtering. This time is from setting the 16/20/24bit data of both channels to input register to the output of analog signal. Note 22. DAC HPL/HPR/LOUT/ROUT/LAUX/RAUX Note 23. LIN HPL/LOUT/LAUX, RIN HPR/ROUT/RAUX
DC CHARACTERISTICS (Ta=25C; AVDD, DVDD, HVDD, PVDD=2.7 3.6V; TVDD=1.6 3.6V) Parameter Symbol min typ max High-Level Input Voltage (2.7V TVDD 3.6V) VIH 70%TVDD VIH 80%TVDD (1.6V TVDD < 2.7V) Low-Level Input Voltage (2.7V TVDD 3.6V) VIL 30%TVDD VIL (1.6V TVDD < 2.7V) 20%TVDD Low-Level Output Voltage (Iout = 3mA) VOL 0.4 Input Leakage Current (Note 24) Iin 10 Note 24. Except I2C and CSN/CAD0 pins. These pins have internal pull-up device, nominally 100k.
Units V V V V V A
MS0506-E-02 - 10 -
2006/07
ASAHI KASEI
[AK4342]
SWITCHING CHARACTERISTICS (Ta=25C; AVDD, DVDD, HVDD, PVDD=2.7 3.6V; TVDD=1.6 3.6V) Parameter Symbol min Master Clock Timing (2.7V TVDD 3.6V) Half Speed Mode (512/768fs) fCLK 4.096 Normal Speed Mode (256/384/512/768fs) fCLK 2.048 Double Speed Mode (128/192/256/384fs) fCLK 6.144 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK Master Clock Timing (1.6V TVDD < 2.7V) fCLK 4.096 Half Speed Mode (512/768fs) fCLK 2.048 Normal Speed Mode (256/384fs) fCLK 6.144 Double Speed Mode (128/192fs) Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK LRCK Timing Frequency 8 fsh Half Speed Mode (DFS1-0 bits = "10") 8 fsn Normal Speed Mode (DFS1-0 bits = "00") 60 fsd Double Speed Mode (DFS1-0 bits = "01") Duty Cycle Duty 45 Serial Interface Timing (Note 25) BICK Period Half Speed Mode tBCK 1/128fsh Normal Speed Mode tBCK 1/128fsn Double Speed Mode tBCK 1/64fsd BICK Pulse Width Low tBCKL 70 Pulse Width High tBCKH 70 (Note 26) tLRB 40 LRCK Edge to BICK "" (Note 26) tBLR 40 BICK "" to LRCK Edge (Note 27) tLRB 40 LRCK Edge to BICK "" (Note 27) tBLR 40 BICK "" to LRCK Edge SDATA Hold Time tSDH 40 SDATA Setup Time tSDS 40 Control Interface Timing (3-wire Serial mode) CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 40 CSN "H" Time tCSW 150 tCSS 50 CSN "" to CCLK "" tCSH 50 CCLK "" to CSN "" Power-down & Reset Timing PDN Pulse Width (Note 28) tPD 150
typ
max 18.432 36.864 36.864 18.432 18.432 18.432 -
Units MHz MHz MHz ns ns MHz MHz MHz ns ns
-
-
-
24 48 96 55
kHz kHz kHz %
-
-
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 25. Refer to "Serial Data Interface". Note 26. When BCKP bit is set to "0", BICK rising edge must not occur at the same time as LRCK edge. Note 27. When BCKP bit is set to "1", BICK falling edge must not occur at the same time as LRCK edge. Note 28. The AK4342 can be reset by bringing PDN pin = "L" to "H" only upon power up.
MS0506-E-02 - 11 -
2006/07
ASAHI KASEI
[AK4342]
SWITCHING CHARACTERISTICS (Continued) (Ta=25C; AVDD, DVDD, HVDD, PVDD=2.7 3.6V; TVDD=2.7 3.6V) Parameter Symbol min typ Control Interface Timing (I2C Bus mode): (Note 29) SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note 30) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Capacitive load on bus Cb Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 Note 29. I2C is a registered trademark of Philips Semiconductors. TVDD voltage must be 2.7V 3.6V in I2C mode. Note 30. Data must be held long enough to bridge the 300ns-transition time of SCL.
max 400 0.3 0.3 400 50
Units kHz s s s s s s s s s s pF ns
MS0506-E-02 - 12 -
2006/07
ASAHI KASEI
[AK4342]
Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Figure 5. Clock Timing
LRCK tBLR tLRB
VIH VIL
BICK tSDS tSDH
VIH VIL
SDATA
VIH VIL
Figure 6. Serial Interface Timing (BCKP bit = "0")
MS0506-E-02 - 13 -
2006/07
ASAHI KASEI
[AK4342]
VIH LRCK tBLR tLRB VIH VIL tSDS tSDH VIH SDATA VIL VIL
BICK
Figure 7. Serial Interface Timing (BCKP bit = "1")
VIH CSN VIL tCSS tCCKL tCCKH VIH VIL tCDS tCDH VIH VIL
CCLK
CDTI
C1
C0
R/W
A4
Figure 8. WRITE Command Input Timing
tCSW VIH CSN VIL tCSH CCLK VIH VIL
CDTI
D3
D2
D1
D0
VIH VIL
Figure 9. WRITE Data Input Timing
MS0506-E-02 - 14 -
2006/07
ASAHI KASEI
[AK4342]
VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop
Figure 10. I2C Bus Mode Timing
tPD
PDN
VIL
Figure 11. Power-down & Reset Timing
MS0506-E-02 - 15 -
2006/07
ASAHI KASEI
[AK4342]
OPERATION OVERVIEW System Clock
The external clocks required to operate the AK4342 are MCLK, BICK and LRCK. MCLK should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter, delta-sigma modulator, charge pump circuit and counter for transition time. The MCLK frequency is detected from the relation between MCLK and LRCK automatically. The Half speed, the Normal speed and the Double speed mode are selected with the DFS1-0 pins (Table 1). The sampling frequency is selected with the FS3-0 bits. (Table 2) When the states of DFS1-0 bits change in the normal operation mode, the AK4342 should be reset by PDN pin or PMDAC bit. DFS1 bit 0 0 1 1 DFS0 bit 0 1 0 1 Mode Normal Speed Double Speed Half Speed fs MCLK Frequency 256/384/512/768fs 8 48kHz 128/192/256/384fs 60 96kHz 512/768fs 8 24kHz Reserve Table 1. System Clock Example
Default
FS3 bit 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS2 bit 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS1 bit FS0 bit Sampling Frequency 0 0 44.1kHz 0 1 32kHz 1 0 48kHz 1 1 (Reserve) 0 0 88.2kHz 0 1 64kHz 1 0 96kHz 1 1 (Reserve) 0 0 22.05kHz 0 1 16kHz 1 0 24kHz 1 1 (Reserve) 0 0 11.025kHz 0 1 8kHz 1 0 12kHz 1 1 (Reserve) Table 2. Set up of Sampling Frequency
Default
For low sampling rates, DR and S/N degrade because of the out-of-band noise. DR and S/N are improved by setting the half speed mode (DFS1-0 bits = "10") S/N (fs=8kHz, 20kLPF + A-weighted) Lineout Headphone Aux-out Normal Speed 89dB 87dB 87dB Half Speed 99dB 95dB 95dB Table 3. Relationship between Clock Mode and S/N of Lineout, Headphone and Aux-out Mode
External clocks (MCLK, BICK and LRCK) should always be present whenever the DAC, headphone amp, lineout amp or charge pump circuits is in normal operation mode (PMDAC bit = "1", PMHP bit = "1", PMLO bit = "1" or PMCP bit = "1"). If these clocks are not provided, the AK4342 is not operated normally, especially, DAC may draw excess current due to dynamic refresh of internal logic. If the external clocks are not present, the DAC, headphone amp, charge pump circuit and lineout amp should be in the power-down mode (PMDAC bit = PMHP bit = PMLO bit = PMCP bit = "0").
MS0506-E-02 - 16 -
2006/07
ASAHI KASEI
[AK4342]
Serial Data Interface
The AK4342 interfaces with external system via the SDATA, BICK and LRCK pins. Five data formats are supported and are selected by the DIF2, DIF1 and DIF0 bits (Table 4). Mode 0 is compatible with existing 16bit DACs and digital filters. Mode 1 is a 20bit version of Mode 0. Mode 4 is a 24bit version of Mode 0. Mode 2 is similar to AKM ADCs and many DSP serial ports. Mode 3 is compatible with the I2S serial data protocol. In Modes 2 and 3 with BICK48fs, the following formats are also valid: 16-bit data followed by eight zeros (17th to 24th bits) and 20-bit data followed by four zeros (21st to 24th bits). In all modes, the serial data is MSB first and 2's complement format. The polarity of BICK can be inverted by the BCKP bit, the polarity of LRCK can be inverted by the LRP bit. PMDAC bit should be set to "0" when BCKP or LRP bits are changed.
DIF2 bit 0 0 0 DIF1 bit 0 0 1 DIF0 bit 0 1 0 MODE 0: 16bit, LSB justified 1: 20bit, LSB justified 2: 24bit, MSB justified
BICK
32fs BICK 128fs (Half/Normal Speed Mode) 32fs BICK 64fs (Double Speed Mode) 40fs BICK 128fs (Half/Normal Speed Mode) 40fs BICK 64fs (Double Speed Mode) 48fs BICK 128fs (Half/Normal Speed Mode) 48fs BICK 64fs (Double Speed Mode) BICK=32fs (Half/Normal/Double Speed Mode) or 48fs BICK 128fs (Half/Normal Speed Mode) 48fs BICK 64fs (Double Speed Mode) 48fs BICK 128fs (Half/Normal Speed Mode) 48fs BICK 64fs (Double Speed Mode)
Figure
Figure 12 Figure 13 Figure 14 Figure 15 Figure 13
Default
0
1
1
3: I2S Compatible
1
0
0
4: 24bit, LSB justified
Table 4. Audio Data Format BCPKP bit 0 0 1 1 LRP bit 0 1 0 1 BICK Polarity LRCK Polarity (SDATA Latch Timing) Lch Data Rch Data H: Mode 0,1,2,4 L: Mode 0,1,2,4 L: Mode 3 H: Mode 3 L: Mode 0,1,2,4 H: Mode 0,1,2,4 H: Mode 3 L: Mode 3 H: Mode 0,1,2,4 L: Mode 0,1,2,4 L: Mode 3 H: Mode 3 L: Mode 0,1,2,4 H: Mode 0,1,2,4 H: Mode 3 L: Mode 3 Table 5. LRCK and BICK Polarities
Default
LRCK BICK (32fs) SDATA Mode 0 BICK SDATA Mode 0
15 14 6 5 4 3 2 1 0 15 14 6 5 4 3 2 1 0 15 14
Don't care 15:MSB, 0:LSB
15
14
0
Don't care
15
14
0
Lch Data
Rch Data
Figure 12. Mode 0 Timing (BCKP bit = "0", LRP bit = "0")
MS0506-E-02 - 17 -
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ASAHI KASEI
[AK4342]
LRCK BICK SDATA Mode 1 SDATA Mode 4
Don't care 19:MSB, 0:LSB Don't care 23:MSB, 0:LSB 23 22 21 20
19
0
Don't care
19
0
19
0
Don't care
23
22
21
20
19
0
Lch Data
Rch Data
Figure 13. Mode 1, 4 Timing (BCKP bit = "0", LRP bit = "0")
LRCK
Lch
Rch
BICK SDATA 16bit SDATA 20bit SDATA 24bit
Figure 14. Mode 2 Timing (BCKP bit = "0", LRP bit = "0")
23 22 8 3 4 1 0 Don't care 23 22 8 3 4 1 0 Don't care 23 22 19 18 4 1 0 Don't care 19 18 4 1 0 Don't care 19 18 15 14 0 Don't care Don't care
15
14
0
15
14
MS0506-E-02 - 18 -
2006/07
ASAHI KASEI
[AK4342]
LRCK BICK SDATA 16bit SDATA 20bit SDATA 24bit
15 14
Lch
Rch
0
Don't care
15
14
0
Don't care
15
19
18
4
1
0
Don't care
19
18
4
1
0
Don't care
19
23
22
8
3
4
1
0
Don't care
23
22
8
3
4
1
0
Don't care
23
BICK (32fs) SDATA 16bit
0 15 14 6 5 4 3 2 1 0 15 14 6 5 4 3 2 1 0 15
Figure 15. Mode 3 Timing (BCKP bit = "0", LRP bit = "0")
MS0506-E-02 - 19 -
2006/07
ASAHI KASEI
[AK4342]
Digital Volume
The AK4342 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE. These volumes are in front of the DAC and can attenuate the input data from 0dB to -48dB and mute. Changing levels are executed via soft changes without any pop noise. The transition time of 1 level and all 256 levels is shown in Table 7. At DATTC bit = "1", ATTL7-0 bits control both Lch and Rch attenuation level, while register values of ATTL7-0 bits are not written to ATTR7-0 bits. At DATTC bit = "0", ATTL7-0 bits control Lch level and ATTR7-0 bits control Rch level. ATTL7-0 bits ATT (dB) ATTR7-0 bits FFH 20 log10 (ATT_DATA / 255) * 01H 00H Mute Table 6. Digital Volume Gain Table
Default
STS1 bit 0
STS0 bit 0
0
1
1
0
1
1
Transition Time 1 Level 255 to 0 Half Speed Mode 1LRCK 255LRCK Normal Speed Mode 2LRCK 510LRCK Double Speed Mode 4LRCK 1020LRCK Half Speed Mode 2LRCK 510LRCK Normal Speed Mode 4LRCK 1020LRCK Double Speed Mode 8LRCK 2040LRCK Half Speed Mode 4LRCK 1020LRCK Normal Speed Mode 8LRCK 2040LRCK Double Speed Mode 16LRCK 4080LRCK Half Speed Mode 8LRCK 2040LRCK Normal Speed Mode 16LRCK 4080LRCK Double Speed Mode 32LRCK 8160LRCK Table 7. Transition Time for Digital Volume Sampling Speed
Default
MS0506-E-02 - 20 -
2006/07
ASAHI KASEI
[AK4342]
Soft Mute
Soft mute operation is performed in the digital domain of the DAC input. When the SMUTE bit goes to "1", the output signal is attenuated by - during ATT_DATAxATT transition time (Figure 16) from the current ATT level. When SMUTE bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATAxATT transition time. If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE bit STS1-0 bits ATT Level Attenuation (1) STS1-0 bits (1) (3)
-
GD (2) Analog Output GD
Figure 16. Soft Mute Function Notes: (1) ATT_DATAxATT transition time. For example, this time is 510LRCK cycles at normal speed mode and STS1-0 bit = "01" and ATT_DATA = "128". (2) Analog output corresponding to digital input has group delay (GD). (3) If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle.
De-emphasis Filter
The AK4342 includes a digital de-emphasis filter (tc = 50/15s) via an IIR filter. This filter corresponds to three frequencies (32kHz, 44.1kHz and 48kHz). This setting is done via control register (DEM1-0 bits). (See Table 8). When the AK4342 is half speed mode or double speed mode, the DEM1-0 bits are ignored and the de-emphasis filter is disabled. DEM1 bit DEM0 bit De-emphasis 0 0 44.1kHz 0 1 OFF 1 0 48kHz 1 1 32kHz Table 8. De-emphasis Filter Frequency control
Default
MS0506-E-02 - 21 -
2006/07
ASAHI KASEI
[AK4342]
Charge Pump Circuit
The internal charge pump circuit generates negative voltage from PVDD voltage. The generated voltage is used to lineout and headphone amplifiers. When PMCP bit is set to "1", the charge pump circuit is powered-up. Then all clocks (MCLK, BICK and LRCK) should be supplied. The power up time of charge pump circuit depends on FS3-0 bits (See Table 9). Power up time of Charge Pump Circuit 0 0 11.6ms 44.1kHz 0 1 8.0ms 32kHz 1 0 10.7ms 48kHz 1 1 (Reserve) (Reserve) 0 0 11.6ms 88.2kHz 0 1 8.0ms 64kHz 1 0 10.7ms 96kHz 1 1 (Reserve) (Reserve) 0 0 11.6ms 22.05kHz 0 1 8.0ms 16kHz 1 0 10.7ms 24kHz 1 1 (Reserve) (Reserve) 0 0 11.6ms 11.025kHz 0 1 8.0ms 8kHz 1 0 10.7ms 12kHz 1 1 (Reserve) (Reserve) Table 9. Power up time of Charge Pump Circuit FS1 bit FS0 bit Sampling Frequency
FS3 bit 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS2 bit 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Default
Analog Input
Signal level from LIN/RIN is adjusted by an external resistor (Ri). Internal feedback resistance (Rf) is 20k 30% . When PMDAC, PMHP, PMLO or PMAUX bit is set to "1", the left and right channel amplifiers are powered-up. The transition time of signal path (LINL, LINR, RINL and RINR bits) is selected by PTS1-0 bits and FS3-0 bits. The signal path (LINL, LINR, RINL and RINR bits) should not be changed during the transition.
Rf = 20k Ri LIN/RIN
+
Figure 17. Block diagram of LIN/RIN inputs
MS0506-E-02 - 22 -
2006/07
ASAHI KASEI
[AK4342]
Headphone Output
Power supply voltage for headphone amplifiers is applied from HVDD and HVEE pins. HVEE pin must be connected with PVEE pin directly. PVEE pin outputs the negative voltage generated by the internal charge pump circuit. The headphone amplifier is single-ended outputs and centered on 0V(HVSS). Therefore, the capacitor for AC-coupling can be removed. The minimum load resistance is 16 . 1. Analog output volume These volumes are channel independent can gain/attenuate the DAC output signal from +6dB to -48dB. (See Table 10) Changing levels don't have any pop noise. The transition time is selected by PTS1-0 bits and sampling frequency (See Table 2 and Table 15). At PGAC bit = "1", PGAL4-0 bits control both Lch and Rch attenuation level, while register values of PGAL4-0 bits are not written to PGAR4-0 bits. At PGAC bit = "0", PGAL4-0 bits control Lch level and PGAR4-0 bits control Rch level. When PGAC bit is changed, the transition of volume is executed via soft changes, and PGAL4-0 and PGAR4-0 bits should be changed after the transition time passes. When changing PGAC bit = "0" "1" (In case of "PGAL4-0 bit PGAR4-0 bit"), the gain of right channel is changed to the register setting of PGAL4-0 bits. When changing PGAC bit = "1" "0" (In case of "PGAL4-0 bit PGAR4-0 bit"), the gain of right channel is changed to the last register setting which is written into PGAR4-0 bits.
PGAL4-0 bits GAIN/ATT (dB) Step Level PGAR4-0 bits 1FH +6 1EH +5 * * 1AH +1 1dB 16 19H 0 18H -1 * * 10H -9 0FH -10 0EH -12 2dB 11 * * 06H -28 05H -30 04H -32 03H -36 4dB 5 02H -40 01H -44 00H -48 Table 10. Volume Setting for headphone amplifier 2. Mute Function
Default
When HMUTEL/HMUTER bit is set to "1", the headphone amplifier (HPL/HPR pins) goes to ground level (0V). This function is independent L/R channels. This mute time depends on the setting of PTS1-0 bits and sampling frequency(FS3-0 bits). When HMUTEL/HMUTER bit is set to "0", the outputs are in normal operation. 3. Power-up/down Headphone amplifiers are powered-up/down by PMHP bit, HPL and HPR pins go to HVSS(0V). The power-on/off time depends on the setting of PUT1-0 bits and sampling frequency (FS3-0 bits). The power-up/down of headphone amplifiers should be done in the mute state (HMUTEL bit = HMUTER bit = "1").
MS0506-E-02 - 23 -
2006/07
ASAHI KASEI
[AK4342]
Lineout amp
Power supply voltage for lineout amplifier is applied from HVDD and HVEE pins. HVEE pin must be connected with PVEE pin directly. PVEE pin outputs the negative voltage generated by the internal charge pump circuit. The lineout amplifiers are single-ended outputs and centered on 0V(HVSS). The output level is typically 2Vrms (@ AVDD=3.3V, 0dBFS). The minimum load resistance is 10k. 1. Analog volume for lineout These volumes are common to L/R channels and can attenuate the DAC output signal from +0dB to -31dB with 1dB step (See Table 11). Changing levels don't have any pop noise. The transition time is selected by PTS1-0 bits and sampling frequency (See Table 2 and Table 15).
LPGA4-0 bits ATT (dB) Step 1FH 0 1EH -1 1DH -2 1CH -3 1dB * * 18H -29 01H -30 00H -31 Table 11. Volume Setting for Lineout 2. Mute Function
Level Default
32
When LMUTE bit is set to "1", the lineout amplifiers (LOUT and ROUT pins) go to ground level (0V). This mute time depends on the setting of PTS1-0 bits and sampling frequency(FS3-0 bits). This function is common to L/R channels. When LMUTE bit is set to "0", the outputs are in normal operation. 3. Power-up/down Lineout amplifiers are powered-up/down by PMLO bit. The power-on/off time depends on the setting of PUT1-0 bits and sampling frequency (FS3-0 bits). The power-up/down of lineout amplifiers should be done in the mute state (LMUTE bit = "1"). 4. Output circuit When LOUT/ROUT drives some capacitive load, a resistor should be added in series between LOUT/ROUT and capacitive load. Figure 18 shows an example of 470 series resistor. In this case, LOUT/ROUT can drive capacitive load up to 1nF.
470
LOUT/ROUT
1n
Analog Out
Figure 18. External 1st order LPF Circuit Example (fc = 339kHz, gain = -0.06dB @ 40kHz)
MS0506-E-02 - 24 -
2006/07
ASAHI KASEI
[AK4342]
Aux-out amp
Aux-out amplifiers are single-ended outputs and centered on VCOM voltage (0.45 x AVDD). Signal output voltage is typically 700mVrms (@ AVDD = 3.3V, 0dBFS). The minimum load resistance is 10k. When the AVCMN bit is set to "0", the common voltage of Aux-out amplifiers falls. When the AVCMN bit is set to "1", the common voltage rises to 0.45 x AVDD. A capacitor between the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant is in proportional to AVDD voltage and the capacitor at MUTET pin. [Example]: A capacitor between the MUTET pin and ground = 1.0F, AVDD=3.3V: Rise/fall time constant: = 100ms(typ), 300ms(max) When PMAUX bit is set to "0", the Aux-out amplifiers are powered-down, and the outputs (LAUX and RAUX pins) go to "L" (AVSS). When the AMUTE bit is set to "1", the outputs (LAUX and RAUX pins) are muted and become VCOM voltage. When the AMUTE bit is set to "0", the outputs are in normal operation.
PMAUX bit
AVCMN bit LAUX pin RAUX pin
(1) (2)
(3)
(4)
Figure 19. Power-up/Power-down Timing for Aux-out amplifier (1) Aux-out amplifier power-up (PMAUX bit = "1"). The outputs are still AVSS. (2) Aux-out amplifier common voltage rises up (AVCMN bit = "1") (3) Aux-out amplifier common voltage falls down (AVCMN bit = "0") (4) Aux-out amplifier power-down (PMAUX bit = "0"). The outputs are AVSS. If the power supply is switched off or Aux-out amplifier is powered-down before the common voltage goes to AVSS, some pop noise occurs.
MS0506-E-02 - 25 -
2006/07
ASAHI KASEI
[AK4342]
Transition Time
Changing volume level, power-up/down and switching signal path don't have any pop noise. The following registers have a transition time shown in Table 13 and Table 15. It depends the sampling frequency (FS3-0 bits) and the setting of PUT1-0 bits and PTS1-0 bits. It is necessary to take the interval time when the register is changed continually. The interval time depends on the transition time. The setting of transition time should not be changed during transition. Address Register Name PUT1-0 bit 00H PMHP, PMLO Table 12. Registers with transition time (PUT1-0 bits) PUT1 bit 0 PUT0 bit 0 Sampling Frequency (FS3-0 bits) 8k / 16k / 32k / 64kHz 11.025k / 22.05k / 44.1k/ 88.2kHz 12k / 24k / 48k / 96kHz 8k / 16k / 32k / 64kHz 11.025k / 22.05k / 44.1k/ 88.2kHz 12k / 24k / 48k / 96kHz 8k / 16k / 32k / 64kHz 11.025k / 22.05k / 44.1k/ 88.2kHz 12k / 24k / 48k / 96kHz 8k / 16k / 32k / 64kHz 11.025k / 22.05k / 44.1k/ 88.2kHz 12k / 24k / 48k / 96kHz Table 13. Transition Time (PUT1-0 bits) Transition Time 32ms 34.8ms 32ms 64ms 69.7ms 64ms 128ms 139ms 128ms 256ms 278ms 256ms
0
1
1
0
Default
1
1
Address Register Name 01H AMUTE 04H HMUTEL, PGAL4-0 PTS1-0 bit 05H HMUTER, PGAR4-0 06H RINR, RINL, LINR, LINL, DACLR 07H LMUTE, LPGA4-0 Table 14. Registers with transition time (PTS1-0 bits) PTS1 bit 0 PTS0 bit 0 Sampling Frequency (FS3-0 bits) 8k / 16k / 32k / 64kHz 11.025k / 22.05k / 44.1k/ 88.2kHz 12k / 24k / 48k / 96kHz 8k / 16k / 32k / 64kHz 11.025k / 22.05k / 44.1k/ 88.2kHz 12k / 24k / 48k / 96kHz 8k / 16k / 32k / 64kHz 11.025k / 22.05k / 44.1k/ 88.2kHz 12k / 24k / 48k / 96kHz 8k / 16k / 32k / 64kHz 11.025k / 22.05k / 44.1k/ 88.2kHz 12k / 24k / 48k / 96kHz Table 15. Transition Time (PTS1-0 bits) Transition Time 16ms 17.4ms 16ms 32ms 34.8ms 32ms 64ms 69.7ms 64ms 128ms 139ms 128ms
Default
0
1
1
0
1
1
MS0506-E-02 - 26 -
2006/07
ASAHI KASEI
[AK4342]
System Reset
PDN pin must keep "L" until all power supply pins (AVDD, DVDD, PVDD, HVDD and TVDD) are applied. After they are applied, PDN pin must be set to "H". After exiting reset (PDN pin: "L" "H"), all blocks (VCOM, DAC, HPL, HPR, LAUX, RAUX, LOUT, ROUT and charge pump circuit) switch to the power-down state. The contents of the control register are maintained until the reset is done. DAC exits reset and power down state by MCLK edge after PMDAC bit is changed to "1", and then DAC is powered up and the internal timing starts clocking by LRCK edge. DAC is in power-down mode until MCLK and LRCK are input.
Power-Up/Down Sequence
Power Supply PDN pin PMVCM bit (3) Clock Input PMCP bit PVEE pin Don't care Don't care (1) (2) (4)
0V
PVEE (10)
0V
PMDAC bit DAC Internal State PMHP bit (or PMLO bit) HMUTEL/R bits (or LMUTE bit) HPL/HPR pins (or LOUT/ROUT pins) 0V MUTE (6) PMLO bit (or PMHP bit) LMUTE bit (or HMUTEL/R bit) LOUT/ROUT pins (or HPL/HPR pins) 0V MUTE (6) (7) Normal MUTE (8) (9) 0V (7) Normal MUTE (8) (9) 0V Power Down (5) Normal Operation Power Down
Figure 20. Example of Power-up/down Sequence (1) After Power Up: PDN pin "L" "H" "L" time (1) of 150ns or more is needed to reset the AK4342. PDN pin must keep "L" until all power supply pins (AVDD, DVDD, PVDD, HVDD and TVDD) are applied. After they are applied, PDN pin must be set to "H". (2) DFS1-0, DIF2-0, DEM1-0, FS3-0, PTS1-0, STS1-0, PUT1-0, LRP, BCKP and DACLR bits should be set during this period before the DAC and charge pump circuit are powered-up. (3) Supply the external clocks (MCLK, BICK, LRCK)
MS0506-E-02 - 27 -
2006/07
ASAHI KASEI
[AK4342]
(4) Power Up the charge pump circuit, DAC and VCOM; PMCP bit = PMDAC bit = PMVCM bit = "0" PVEE pin goes to PVEE voltage according to the setting of FS3-0 bits (See Table 9).
"1"
(5) When PMCP bit and PMHP bit (PMLO bit) are set to "1" at the same time or PMHP bit (PMLO bit) is set to "1" during the charge pump circuit is powered-up, headphone (lineout) amplifier is powered-up after the charge pump circuit is powered-up. (6) Power Up the headphone (lineout) amplifiers; PMHP bit (PMLO bit) = "0" "1" The headphone (lineout) amplifiers are in mute state and have some DC offset. The power up time of headphone (lineout) amplifiers depends on PUT1-0 bits and FS3-0 bits. PMHP and PMLO bits should not be changed during this period. (7) Release the mute state of headphone (lineout) amplifiers; HMUTEL bit = HMUTER bit (LMUTE bit) = "1" "0" The headphone (lineout) amplifiers are in the normal state after the transition time passes. The transition is executed via soft changes. The transition time depends on PTS1-0 bits and FS3-0 bits. LPGA4-0, PGAL4-0, PGAR4-0 and PGAC bits should not be changed during this period. (8) Mute headphone (lineout) amplifiers: HMUTEL = HMUTER (LMUTE bit) = "0" "1" The headphone (lineout) amplifiers are in the mute state after the transition time passes. The transition is executed via soft changes. The transition time depends on PTS1-0 bits and FS3-0 bits. LPGA4-0, PGAL4-0, PGAR4-0 and PGAC bits should not be changed during this period. (9) Power-down the headphone (lineout) amp; PMHP bit (PMLO bit) = "1" "0" The headphone (lineout) amplifiers are powered-down. The power-down time of headphone (lineout) amplifiers depend on PUT1-0 bits and FS3-0 bits. PMHP and PMLO bits should not be changed during this period. (10) Power down the charge pump circuit, DAC and VCOM; PMCP bit = PMDAC bit = PMVCM bit = "1" "0" PVEE pin becomes "0V" according to the time constant of internal resistor and capacitor of PVEE and HVEE pins. Internal resistor is typically 17.5k. The charge pump circuit may be powered-up during this period.
MS0506-E-02 - 28 -
2006/07
ASAHI KASEI
[AK4342]
Serial Control Interface 1. 3-wire Serial Control Mode (I2C pin = "L")
Internal registers may be written by using the 3-wire P interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 2-bit Chip address (Fixed to "01"), Read/Write (Fixed to "1"), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge ("") of CCLK. Address and data are latched on the CSN falling edge (""). Clock speed of CCLK is 5MHz (max). The value of internal registers are initialized by PDN pin = "L".
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: R/W: A4-A0: D7-D0:
Chip Address (Fixed to "01") READ/WRITE (Fixed to "1", Write only) Register Address Control Data
Figure 21. Serial Control I/F Timing
MS0506-E-02 - 29 -
2006/07
ASAHI KASEI
[AK4342]
2. I2C-bus Control Mode (I2C pin = "H")
The AK4342 supports a fast-mode I2C-bus system (max: 400kHz). 1. WRITE Operations Figure 22 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 28). After the START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit (R/W). The most significant five bits of the slave address are fixed as "001000". The next one bit is CAD0 (device address bit). This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) set these device address bits (Figure 23). If the slave address matches that of the AK4342, the AK4342 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 29). A R/W bit value of "1" indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4342. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 24). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 25). The AK4342 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 28). The AK4342 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4342 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 09H prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 30) except for the START and STOP conditions.
S T A R T
R/W="0"
S T O P Sub Address(n) Data(n) A C K A C K Data(n+1) A C K A C K Data(n+x) A C K P
SDA
Slave S Address A C K
Figure 22. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
0
CAD0
R/W
Figure 23. The First Byte
0
0
0
A4
A3
A2
A1
A0
Figure 24. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 25. Byte Structure after the second byte
MS0506-E-02 - 30 -
2006/07
ASAHI KASEI
[AK4342]
2. READ Operations Set the R/W bit = "1" for the READ operation of the AK4342. After transmission of data, the master can read the next address's data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 09H prior to generating a stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The AK4342 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. 2-1. CURRENT ADDRESS READ The AK4342 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to "1", the AK4342 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4342 ceases transmission.
S T A R T
R/W="1"
S T O P Data(n) Data(n+1) A C K A C K Data(n+2) A C K A C K Data(n+x) A C K P
SDA
Slave S Address A C K
Figure 26. CURRENT ADDRESS READ 2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues a start request, a slave address (R/W bit = "0") and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit set to "1". The AK4342 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4342 ceases transmission.
S T A R T S T A R T Sub Address(n) A C K A C K
R/W="0"
R/W="1"
S T O P Data(n) Data(n+1) A C K A C K A C K Data(n+x) A C K P
SDA
Slave S Address
Slave S Address A C K
Figure 27. RANDOM ADDRESS READ
MS0506-E-02 - 31 -
2006/07
ASAHI KASEI
[AK4342]
SDA
SCL S start condition P stop condition
Figure 28. START and STOP Conditions
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S clock pulse for acknowledgement
1
2
8
9
START CONDITION
Figure 29. Acknowledge on the I2C-Bus
SDA
SCL
data line stable; data valid
change of data allowed
Figure 30. Bit Transfer on the I2C-Bus
MS0506-E-02 - 32 -
2006/07
ASAHI KASEI
[AK4342]
Register Map
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H Register Name Power Management Mode Control 0 Mode Control 1 Mode Control 2 HP Lch PGA Control HP Rch PGA Control Output Select Lineout PGA control DAC Lch ATT DAC Rch ATT D7
0
AMUTE
D6
0 SMUTE
D5
PMAUX AVCMN FS3 PTS0 HMUTEL HMUTER RINR LMUTE ATTL5 ATTR5
D4
PMLO DIF2 FS2 STS1 PGAL4 PGAR4 RINL LPGA4 ATTL4 ATTR4
D3
PMCP DIF1 FS1 STS0 PGAL3 PGAR3 LINR LPGA3 ATTL3 ATTR3
D2
PMHP DIF0 FS0 DATTC PGAL2 PGAR2 LINL LPGA2 ATTL2 ATTR2
D1
PMDAC DFS1 DEM1 BCKP PGAL1 PGAR1 DACLR LPGA1 ATTL1 ATTR1
D0
PMVCM
0
PGAC 0 0 PUT1 0 ATTL7 ATTR7
0
PTS1 0 0 PUT0 0 ATTL6 ATTR6
DFS0 DEM0 LRP PGAL0 PGAR0 0 LPGA0 ATTL0 ATTR0
All registers inhibit writing at PDN pin = "L". PDN pin = "L" resets the registers to their default values. Note 31: The bits indicated to "0" in the register map must contain a "0" value. Note 32: Only write to address 00H to 09H.
MS0506-E-02 - 33 -
2006/07
ASAHI KASEI
[AK4342]
Register Definitions
Addr 00H Register Name Power Management R/W Default D7 0 RD 0 D6
0
D5
PMAUX
RD 0
R/W 0
D4 PMLO R/W 0
D3 PMCP R/W 0
D2
PMHP
D1
PMDAC
D0
PMVCM
R/W 0
R/W 0
R/W 0
PMVCM: Power Management for VCOM Block 0: Power OFF (Default) 1: Power ON PMDAC: Power Management for DAC Blocks 0: Power OFF (Default) 1: Power ON When PMDAC bit is changed from "0" to "1", DAC is powered-up with the current register values (ATT value, sampling rate, etc). PMHP: Power Management for Headphone Amp 0: Power OFF (Default). HPL/HPR pins become HVSS (0V). 1: Power ON PMCP: Power Management for Charge Pump Circuit 0: Power OFF (Default) 1: Power ON PMLO: Power Management for Line-out Amp 0: Power OFF (Default). LOUT/ROUT pins become HVSS (0V). 1: Power ON PMAUX: Power Management for Aux Out 0: Power OFF (Default) LAUX and RAUAX pins become AVSS (0V). 1: Power ON All blocks can be powered-down by setting the PDN pin to "L" regardless of register values setup. All blocks can be also powered-down by setting all bits of this address to "0". In this case, control register values are maintained.
MS0506-E-02 - 34 -
2006/07
ASAHI KASEI
[AK4342]
Addr 01H
Register Name Mode Control 0 R/W Default
D7
AMUTE
D6
SMUTE
D5
AVCMN
R/W 1
R/W 0
R/W 0
D4 DIF2 R/W 0
D3 DIF1 R/W 1
D2 DIF0 R/W 0
D1 DFS1 R/W 0
D0 DFS0 R/W 0
DFS1-0: Sampling Speed Select (See Table 1) Default: "00" (Normal Speed Mode) DIF2-0: Audio Data Interface Format Select (See Table 4) Default: "010" (Mode 2; 24bit, MSB justified) AVCMN: Common Voltage control for LAUX/RAUX 0: LAUX/RAUX pins become AVSS (0V). (Default) 1: LAUX/RAUX pins become "0.45 x AVDD". SMUTE: Soft Mute Control 0: Normal operation (Default) 1: DAC outputs soft-muted AMUTE: Mute control for LAUX/RAUX 0: Normal operation 1: Mute. LAUX/RAUX pins output common voltage. (Default)
Addr 02H
Register Name Mode Control 1 R/W Default
D7 0 RD 0
D6 0 RD 0
D5 FS3 R/W 0
D4 FS2 R/W 0
D3 FS1 R/W 0
D2 FS0 R/W 0
D1 DEM1 R/W 0
D0 DEM0 R/W 1
DEM1-0: De-emphasis Filter Frequency Select (See Table 8) Default: "01" (OFF) FS3-0: Sampling Frequency Select (Table 2) Default: "0000" (fs=44.1kHz)
MS0506-E-02 - 35 -
2006/07
ASAHI KASEI
[AK4342]
Addr 03H
Register Name Mode Control 2 R/W Default
D7 PGAC R/W 0
D6 PTS1 R/W 0
D5 PTS0 R/W 0
D4 STS1 R/W 0
D3 STS0 R/W 1
D2
DATTC
R/W 0
D1 BCKP R/W 0
D0 LRP R/W 0
LRP: LRCK Polarity Select 0: Normal (Default) 1: Invert BCKP: BICK Polarity Select 0: Normal (Default) 1: Invert DATTC: DAC Digital Attenuator Control Mode Select 0: Independent (Default) 1: Dependent At DATTC bit = "1", ATTL7-0 bits control both Lch and Rch attenuation level, while register values of ATTL7-0 bits are not written to ATTR7-0 bits. At DATTC bit = "0", ATTL7-0 bits control Lch level and ATTR7-0 bits control Rch level. STS1-0: Soft mute cycle setting (See Table 7) Default: "01" (1020LRCK at Normal Speed Mode) PTS1-0: Select Transition time for AMUTE, LINL, LINR, RINL, RINR, DACLR, LPGA4-0, PGAL4-0, PGAR4-0, LMUTE, HMUTEL and HMUTER (See Table 15) Default: "00" PGAC: PGA Control Mode Select 0: Independent (Default) 1: Dependent At PGAC bit = "1", PGL4-0 bits control both Lch and Rch attenuation level, while register values of PGAL4-0 bits are not written to PGAR4-0 bits. At PGAC bit = "0", PGAL4-0 bits control Lch level and PGAR4-0 bits control Rch level.
Addr 04H 05H
Register Name Lch PGA Control Rch PGA Control R/W Default
D7 0 0 RD 0
D6 0 0 RD 0
D5
HMUTEL HMUTER
R/W 1
D4 PGAL4 PGAR4 R/W 1
D3 PGAL3 PGAR3 R/W 1
D2 PGAL2 PGAR2 R/W 0
D1 PGAL1 PGAR1 R/W 0
D0 PGAL0 PGAR0 R/W 1
PGAL4-0: Setting of analog volume for Lch (See Table 10) HMUTEL: Mute control for HPL 0: Normal operation PGAL4-0 bits control attenuation value. 1: Mute. (Default) PGAL4-0 bits are ignored. PGAR4-0: Setting of analog volume for Rch (See Table 10) HMUTER: Mute control for HPR 0: Normal operation PGAR4-0 bits control attenuation value. 1: Mute. (Default) PGAR4-0 bits are ignored.
MS0506-E-02 - 36 -
2006/07
ASAHI KASEI
[AK4342]
Addr 06H
Register Name Output Select 0 R/W Default
D7 PUT1 R/W 1
D6 PUT0 R/W 0
D5 RINR R/W 0
D4 RINL R/W 0
D3 LINR R/W 0
D2 LINL R/W 0
D1
DACLR
R/W 0
D0 0 RD 0
DACLR: DAC output signal is added to MIX amp. 0: OFF (Default) 1: ON LINL: Input signal to LIN pin is added to Lch of MIX amp. 0: OFF (Default) 1: ON LINR: Input signal to LIN pin is added to Rch of MIX amp. 0: OFF (Default) 1: ON RINL: Input signal to RIN pin is added to Lch of MIX amp. 0: OFF (Default) 1: ON RINR: Input signal to RIN pin is added to Rch of MIX amp. 0: OFF (Default) 1: ON PUT1-0: Select Transition Time for PMHP and PMLO bits (See Table 13) Defaults: "10"
20k(typ) Ri LIN
+
LINL bit
R R R
RINL bit
+
Lch MIX-Amp
To Lch output buffers
R
DAC(Lch)
DACLR bit
R
DAC(Rch)
RIN 20k(typ)
LINR bit
R R
+
Rch MIX-Amp
To Rch output buffers
Ri
+
RINR bit
R
Figure 31. Analog Mixing Circuit
MS0506-E-02 - 37 -
2006/07
ASAHI KASEI
[AK4342]
Addr 07H
Register Name Lineout PGA Control R/W Default
D7 0 RD 0
D6 0 RD 0
D5 LMUTE R/W 1
D4 LPGA4 R/W 1
D3 LPGA3 R/W 1
D2 LPGA2 R/W 1
D1 LPGA1 R/W 1
D0 LPGA0 R/W 1
LPGA4-0: Setting of the analog volume for Lineout Default: "1FH" (0dB) (See Table 11) LMUTE: Mute control for LOUT/ROUT 0: Normal operation LPGA4-0 bits control attenuation value. 1: Mute. (Default) LPGA4-0 bits are ignored.
Addr 08H 09H
Register Name DAC Lch ATT DAC Rch ATT R/W Default
D7 ATTL7 ATTR7 R/W 1
D6 ATTL6 ATTR6 R/W 1
D5 ATTL5 ATTR5 R/W 1
D4 ATTL4 ATTR4 R/W 1
D3 ATTL3 ATTR3 R/W 1
D2 ATTL2 ATTR2 R/W 1
D1 ATTL1 ATTR1 R/W 1
D0 ATTL0 ATTR0 R/W 1
ATTL7-0: Setting of the attenuation value of output signal from DAC Lch ATTR7-0: Setting of the attenuation value of output signal from DAC Rch ATT = 20 log10 (ATT_DATA / 255) [dB] FFH: 0dB (Default) 00H: Mute
MS0506-E-02 - 38 -
2006/07
ASAHI KASEI
[AK4342]
SYSTEM DESIGN
Figure 32 shows the system connection diagram. An evaluation board [AKD4342] is available which demonstrates the optimum layout, power supply arrangements and measurement results.
Analog Input Aux-out 10u + Lineout
Power Supply 2.7 3.6V
0.1u
24
23
22
21
20
19
18
RAUX
1u 25 MUTET 0.1u 2.2u + 26 VCOM 0.1u 27 AVDD 10 28 AVSS 0.1u 29 DVSS 30 DVDD
HVDD
ROUT
HVSS
LOUT
LAUX
RIN
LIN
17
HPR HPL HVEE
16 Headphone 15 14 13 12 11 10 9 2.2u (+):Note 0.1u 2.2u (+):Note
AK4342EN
Top View
PVEE PVSS PVDD CN
Power Supply 1.6 3.6V
+ 10u 0.1u
31 TVDD SDA/CDTI 32 I2C CAD0/CSN SCL/CCLK
CP SDATA MCLK LRCK BICK PDN
Digital Ground
Analog Ground
1
2
3
4
5
6
7
P
DSP
Figure 32. Typical Connection Diagram in 3-wire mode Note: -
A 2 resistor should be added in series between HVDD/PVDD pins and power supply line in order to limit the current. These capacitors should use low ESR (Equivalent Series Resistance) over all temperature range. When these capacitors are not bipolar, the positive side should be connected CP pin or analog ground. AVSS, DVSS, PVSS and HVSS of the AK4342 should be distributed separately from the ground of external controllers. All digital input except for pull-up pins should not be left floating. If TVDD voltage is the same as DVDD voltage, TVDD pin is directly connected to DVDD pin and the capacitor (10F and 0.1F) connected to TVDD pin can be removed.
MS0506-E-02 - 39 -
8
2
2006/07
ASAHI KASEI
[AK4342]
PACKAGE
32pin QFN (Unit: mm)
5.00 0.10 4.75 0.10 24 25 5.00 0.10 4.75 0.10 17 16
B
0.40 0.10 3.5 24 25
32 1 0.23
+0.07 -0.05
9 8 0.50
A
Exposed Pad
32
2 .4 C0
1
0.10
M
AB
0.85 0.05
C
0.08 C
Note) The exposed pad on the bottom surface of the package must be connected to the ground.
Package & Lead frame material
Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate
MS0506-E-02 - 40 -
0.04 0.01+ 0.01 -
0.20
3.5
2006/07
ASAHI KASEI
[AK4342]
MARKING
4342
XXXX
1
XXXXX : Date code identifier (4 digits)
MS0506-E-02 - 41 -
2006/07
ASAHI KASEI
[AK4342]
Revision History
Date (YY/MM/DD) 06/04/26 06/05/09 Revision 00 01 Reason First Edition Change description Page 39 Contents SYSTEM DESIGN: Figure 32: A 2 resistor was added between PVDD and HVDD pins and power supply line. Note: "A 2 resistor should be added in series the current." was added. ANALOG CHARACTERISTICS: Headphone-Amp; THD+N (fs=44.1kHz, 0dBFS output): typ. -20dB -40dB THD+N (fs=96kHz, 0dBFS output): typ. -20dB -40dB Line Output; THD+N (fs=96kHz, 0dBFS output): typ. -85dB -88dB Headphone Output 1. Analog output volume; See Table 12 and Table 15 See Table 2 and Table 15 Lineout amp 1. Analog volume for lineout; See Table 12 and Table 15 See Table 2 and Table 15 Aux-out amp Figure 19: (2) [AVCMN bit = "0"] [AVCMN bit = "1"] (3) [AVCMN bit = "1"] [AVCMN bit ="0"] Power-Up/Down Sequence: Figure 20; The location of (4) in Figure 20 was changed. 3-wire Serial Control Mode: 2-bit Chip address (Fixed to "10") 2-bit Chip address (Fixed to "01") I2C -bus Control Mode: a. [The AK4342 supports (max.100kHz).] was deleted. b. [The AK4342 does not support a fast-mode I2C-bus system (max.400kHz).] [The AK4342 supports a fast-mode I2C-bus system (max.400kHz).] c. WRITE Operations; [If the address exceeds 08H prior to . ] [If the address exceeds 09H prior to .] Addr=06H, PUT1-0: See Table 12 See Table 13
06/07/07
02
Error Correct
7
23
24
25
27
29
30
37
MS0506-E-02 - 42 -
2006/07
ASAHI KASEI
[AK4342]
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0506-E-02 - 43 -
2006/07

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